{"id":6645,"date":"2025-11-18T16:02:52","date_gmt":"2025-11-18T08:02:52","guid":{"rendered":"https:\/\/www.lxbchip.com\/?post_type=product&p=6645"},"modified":"2026-01-29T19:09:18","modified_gmt":"2026-01-29T11:09:18","slug":"xc4vlx25-10sfg363i","status":"publish","type":"product","link":"https:\/\/www.lxbchip.com\/vi\/products\/xc4vlx25-10sfg363i\/","title":{"rendered":"XC4VLX25-10SFG363I"},"content":{"rendered":"\n\n\n\n\n
M\u00c3 S\u1ea2N PH\u1ea8M<\/th>\nB\u1ed8 PHIM<\/th>\nS\u1ed0 L\u01af\u1ee2NG PH\u00d2NG TH\u00cd NGHI\u1ec6M\/CLBS<\/th>\n\u0110\u1ed8 B\u1ec0N THEO T\u1ed0C \u0110\u1ed8<\/th>\nS\u1ed0 L\u01af\u1ee2NG PH\u1ea6N T\u1eec L\u1ed0I \/ T\u1ebe B\u00c0O<\/th>\nT\u1ed5ng s\u1ed1 bit RAM<\/th>\nS\u1ed0 L\u01af\u1ee2NG I\/O<\/th>\n\u0110i\u1ec7n \u00e1p \u2013 Ngu\u1ed3n c\u1ea5p<\/th>\nLo\u1ea1i l\u1eafp \u0111\u1eb7t<\/th>\nNHI\u1ec6T \u0110\u1ed8 HO\u1ea0T \u0110\u1ed8NG<\/th>\nG\u00d3I \/ H\u1ed8P<\/th>\nG\u00d3I THI\u1ebeT B\u1eca C\u1ee6A NH\u00c0 CUNG C\u1ea4P<\/th>\n<\/tr>\n<\/thead>\n
XC4VLX25-10SFG363I<\/td>\nVirtex-4 SX<\/td>\n0,00<\/td>\n-10,00<\/td>\n\u2014<\/td>\n\u2014<\/td>\n240<\/td>\n1,14 V ~ 1,26 V<\/td>\nL\u1eafp \u0111\u1eb7t b\u1ec1 m\u1eb7t<\/td>\n\u2014<\/td>\n363-FBGA, FCBGA<\/td>\n363-FCBGA (17\u00d717)<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

XC4VLX25-10SFG363I: Vi m\u1ea1ch Virtex-4 LX c\u1ea5p c\u00f4ng nghi\u1ec7p trong v\u1ecf SF363 nh\u1ecf g\u1ecdn<\/strong><\/span><\/p>\n

The XC4VLX25-10SFG363I<\/b> cung c\u1ea5p 24.192 \u00f4 logic trong m\u1ed9t thi\u1ebft k\u1ebf nh\u1ecf g\u1ecdn 17 mm \u00d7 17 mm<\/b> di\u1ec7n t\u00edch chi\u1ebfm d\u1ee5ng. \u0110\u01b0\u1ee3c thi\u1ebft k\u1ebf cho c\u00e1c \u1ee9ng d\u1ee5ng c\u00f4ng nghi\u1ec7p n\u01a1i di\u1ec7n t\u00edch bo m\u1ea1ch in (PCB) b\u1ecb h\u1ea1n ch\u1ebf nh\u01b0ng kh\u1ea3 n\u0103ng ch\u1ecbu \u0111\u1ef1ng m\u00f4i tr\u01b0\u1eddng l\u00e0 y\u00eau c\u1ea7u b\u1eaft bu\u1ed9c, FPGA n\u00e0y gi\u00fap gi\u1ea3i quy\u1ebft m\u00e2u thu\u1eabn gi\u1eefa logic m\u1eadt \u0111\u1ed9 cao v\u00e0 thi\u1ebft k\u1ebf k\u00edch th\u01b0\u1edbc nh\u1ecf g\u1ecdn.<\/p>\n

S\u1ef1 k\u1ebft h\u1ee3p gi\u1eefa Ph\u1ea1m vi nhi\u1ec7t \u0111\u1ed9 c\u00f4ng nghi\u1ec7p<\/b> v\u00e0 -10 b\u1eadc \u0111\u1ed9 d\u1ed1c<\/b> \u0111i\u1ec1u n\u00e0y khi\u1ebfn b\u1ed9 ph\u1eadn n\u00e0y \u0111\u1eb7c bi\u1ec7t ph\u00f9 h\u1ee3p cho c\u00e1c \u1ee9ng d\u1ee5ng d\u00e0i h\u1ea1n trong l\u0129nh v\u1ef1c vi\u1ec5n th\u00f4ng ngo\u00e0i tr\u1eddi, h\u1ec7 th\u1ed1ng t\u00edn hi\u1ec7u \u0111\u01b0\u1eddng s\u1eaft v\u00e0 t\u1ef1 \u0111\u1ed9ng h\u00f3a c\u00f4ng nghi\u1ec7p ch\u1ecbu va \u0111\u1eadp m\u1ea1nh, n\u01a1i \u0111\u1ed9 tin c\u1eady \u0111\u01b0\u1ee3c \u01b0u ti\u00ean h\u01a1n t\u1ed1c \u0111\u1ed9 xung nh\u1ecbp thu\u1ea7n t\u00fay.<\/p>\n

Th\u00f4ng s\u1ed1 k\u1ef9 thu\u1eadt ch\u00ednh<\/span><\/strong><\/p>\n

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    T\u1ebf b\u00e0o logic:<\/b> 24,192<\/p>\n<\/li>\n

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    M\u1ea3ng CLB:<\/b> 48 x 72<\/p>\n<\/li>\n

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    T\u1ed5ng dung l\u01b0\u1ee3ng RAM kh\u1ed1i:<\/b> 1.296 KB<\/p>\n<\/li>\n

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    C\u00e1c nh\u00f3m nh\u1ecf c\u1ee7a DSP48:<\/b> 48<\/p>\n<\/li>\n

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    Giao ti\u1ebfp ng\u01b0\u1eddi d\u00f9ng:<\/b> 240 (T\u1ed1i \u0111a)<\/p>\n<\/li>\n

  • \n

    G\u00f3i:<\/b> SFG363 (BGA kho\u1ea3ng c\u00e1ch ch\u00e2n nh\u1ecf, kho\u1ea3ng c\u00e1ch 0,8 mm, kh\u00f4ng ch\u1ee9a ch\u00ec)<\/p>\n<\/li>\n

  • \n

    \u0110\u00e1nh gi\u00e1 t\u1ed1c \u0111\u1ed9:<\/b> -10<\/p>\n<\/li>\n

  • \n

    C\u1ea5p \u0111\u1ed9 nhi\u1ec7t \u0111\u1ed9:<\/b> C\u00f4ng nghi\u1ec7p ($-40\u00b0C$<\/span> \u0111\u1ebfn $ + 100\u00b0C $<\/span> $T_j$<\/span>)<\/p>\n<\/li>\n<\/ul>\n

    C\u00e1c y\u1ebfu t\u1ed1 c\u1ea7n l\u01b0u \u00fd trong thi\u1ebft k\u1ebf ph\u1ea7n c\u1ee9ng<\/span><\/strong><\/p>\n