{"id":10301,"date":"2026-01-15T15:10:58","date_gmt":"2026-01-15T07:10:58","guid":{"rendered":"https:\/\/www.lxbchip.com\/?page_id=10301"},"modified":"2026-04-09T02:11:49","modified_gmt":"2026-04-08T18:11:49","slug":"rockchip","status":"publish","type":"page","link":"https:\/\/www.lxbchip.com\/vi\/manufacturers\/rockchip\/","title":{"rendered":"ROCKCHIP"},"content":{"rendered":"<div class=\"wpb-content-wrapper\"><div class=\"vc_row wpb_row vc_row-fluid vc_custom_1768800104178 wd-rs-696dbf566a791\"><div class=\"wpb_column vc_column_container vc_col-sm-12\"><div class=\"vc_column-inner\"><div class=\"wpb_wrapper\">\n\t\t<div id=\"wd-696dd476e844f\" class=\"title-wrapper wd-wpb wd-set-mb reset-last-child  wd-rs-696dd476e844f wd-title-color-default wd-title-style-default text-left  wd-underline-colored\">\n\t\t\t\n\t\t\t<div class=\"liner-continer\">\n\t\t\t\t<h2 class=\"woodmart-title-container title  wd-font-weight- wd-fontsize-xl\" >Gi\u1ea3i ph\u00e1p ROCKCHIP c\u1ee7a LXB Semicon<\/h2>\n\t\t\t\t\t\t\t<\/div>\n\t\t\t\n\t\t\t\t\t\t\t<div class=\"title-after_title reset-last-child  wd-fontsize-s\">LXB Semicon cung c\u1ea5p d\u1ecbch v\u1ee5 ph\u00e2n ph\u1ed1i chuy\u00ean nghi\u1ec7p c\u00e1c b\u1ed9 vi x\u1eed l\u00fd h\u1ec7 th\u1ed1ng (SoC) hi\u1ec7u su\u1ea5t cao v\u00e0 gi\u1ea3i ph\u00e1p nh\u00fang c\u1ee7a ROCKCHIP, \u0111\u1ea3m b\u1ea3o ngu\u1ed3n cung \u1ed5n \u0111\u1ecbnh cho c\u00e1c \u1ee9ng d\u1ee5ng c\u00f4ng nghi\u1ec7p, \u00f4 t\u00f4 v\u00e0 ti\u00eau d\u00f9ng.<\/div>\n\t\t\t\n\t\t\t\n\t\t<\/div>\n\t\t\n\t\t<\/div><\/div><\/div><\/div>\n<p>&nbsp;<\/p>\n<table width=\"4574\">\n<tbody>\n<tr>\n<td width=\"142\">Ph\u1ee5 t\u00f9ng c\u1ee7a nh\u00e0 s\u1ea3n xu\u1ea5t<\/td>\n<td width=\"85\">B\u1ea3ng d\u1eef li\u1ec7u<\/td>\n<td width=\"113\">Nh\u00e0 s\u1ea3n xu\u1ea5t<\/td>\n<td width=\"170\">C\u00f4ng ngh\u1ec7 quy tr\u00ecnh<\/td>\n<td width=\"227\">S\u1ed1 l\u00f5i CPU &amp; Ki\u1ebfn tr\u00fac<\/td>\n<td width=\"161\">T\u1ea7n s\u1ed1 t\u1ed1i \u0111a c\u1ee7a CPU<\/td>\n<td width=\"293\">B\u1ed9 nh\u1edb \u0111\u1ec7m L1\/L2<\/td>\n<td width=\"85\">B\u1ed9 x\u1eed l\u00fd \u0111\u1ed3 h\u1ecda<\/td>\n<td width=\"378\">H\u1ed7 tr\u1ee3 giao di\u1ec7n l\u1eadp tr\u00ecnh \u1ee9ng d\u1ee5ng \u0111\u1ed3 h\u1ecda (Graphics API)<\/td>\n<td width=\"359\">B\u1ed9 gi\u1ea3i m\u00e3 \u0111a ph\u01b0\u01a1ng ti\u1ec7n<\/td>\n<td width=\"378\">Giao di\u1ec7n hi\u1ec3n th\u1ecb<\/td>\n<td width=\"350\">Giao di\u1ec7n b\u1ed9 nh\u1edb<\/td>\n<td width=\"378\">H\u1ed7 tr\u1ee3 m\u00e3 h\u00f3a video<\/td>\n<td width=\"378\">T\u00ednh n\u0103ng b\u1ea3o m\u1eadt<\/td>\n<td width=\"378\">Giao di\u1ec7n k\u1ebft n\u1ed1i<\/td>\n<td width=\"321\">G\u00f3i<\/td>\n<td width=\"378\">S\u1eed d\u1ee5ng th\u00f4ng th\u01b0\u1eddng<\/td>\n<\/tr>\n<tr>\n<td><\/td>\n<td><\/td>\n<td><\/td>\n<td><\/td>\n<td><\/td>\n<td><\/td>\n<td><\/td>\n<td><\/td>\n<td><\/td>\n<td><\/td>\n<td><\/td>\n<td><\/td>\n<td><\/td>\n<td><\/td>\n<td><\/td>\n<td><\/td>\n<td><\/td>\n<\/tr>\n<tr>\n<td>Rockchip RK3288<\/td>\n<td><\/td>\n<td>ROCKCHIP<\/td>\n<td>28 nanomet<\/td>\n<td>B\u1ed9 x\u1eed l\u00fd b\u1ed1n nh\u00e2n ARM Cortex-A17<\/td>\n<td>L\u00ean \u0111\u1ebfn 1,8 GHz<\/td>\n<td>L1: 4\u00d732 KB; L2: 1 MB (th\u00f4ng th\u01b0\u1eddng)<\/td>\n<td>Mali-T764<\/td>\n<td>OpenGL ES 1.1\/2.0\/3.1, OpenCL, DirectX 9.3<\/td>\n<td>B\u1ed9 gi\u1ea3i m\u00e3 4K 10-bit H.265\/H.264 + 1080p<\/td>\n<td>RGB, Dual LVDS, Dual MIPI-DSI, eDP, HDMI 2.0 (4K@60Hz)<\/td>\n<td>K\u00eanh \u0111\u00f4i DDR3\/DDR3L\/LPDDR2\/LPDDR3<\/td>\n<td>Gi\u1ea3i m\u00e3 H.264, H.265 4K; B\u1ed9 m\u00e3 h\u00f3a 1080p<\/td>\n<td>ARM TrustZone, \u0110\u01b0\u1eddng d\u1eabn video an to\u00e0n, M\u00e3 h\u00f3a, Kh\u1edfi \u0111\u1ed9ng an to\u00e0n<\/td>\n<td>HDMI, Ethernet MAC, USB, SPI, UART, I2C, I2S, PS2, CSI-2, SDIO<\/td>\n<td>BGA636 (19 \u00d7 19 mm, kho\u1ea3ng c\u00e1ch ch\u00e2n 0,65 mm)<\/td>\n<td>T\u00ednh to\u00e1n nh\u00fang, m\u00e1y t\u00ednh b\u1ea3ng, m\u00e0n h\u00ecnh, \u0111\u1ea7u thu k\u1ef9 thu\u1eadt s\u1ed1 (STB), c\u00f4ng nghi\u1ec7p<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/div>","protected":false},"excerpt":{"rendered":"<p>&nbsp; Mfr Part Datasheet Manufacturer Process Technology CPU Cores &amp; Architecture CPU Max Frequency L1\/L2 Cache GPU Graphics API Support<\/p>","protected":false},"author":1,"featured_media":0,"parent":388,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_acf_changed":false,"footnotes":""},"class_list":["post-10301","page","type-page","status-publish","hentry"],"acf":[],"aioseo_notices":[],"_links":{"self":[{"href":"https:\/\/www.lxbchip.com\/vi\/wp-json\/wp\/v2\/pages\/10301","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.lxbchip.com\/vi\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.lxbchip.com\/vi\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.lxbchip.com\/vi\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.lxbchip.com\/vi\/wp-json\/wp\/v2\/comments?post=10301"}],"version-history":[{"count":0,"href":"https:\/\/www.lxbchip.com\/vi\/wp-json\/wp\/v2\/pages\/10301\/revisions"}],"up":[{"embeddable":true,"href":"https:\/\/www.lxbchip.com\/vi\/wp-json\/wp\/v2\/pages\/388"}],"wp:attachment":[{"href":"https:\/\/www.lxbchip.com\/vi\/wp-json\/wp\/v2\/media?parent=10301"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}