{"id":6662,"date":"2025-11-18T16:33:30","date_gmt":"2025-11-18T08:33:30","guid":{"rendered":"https:\/\/www.lxbchip.com\/?post_type=product&#038;p=6662"},"modified":"2026-02-02T19:39:50","modified_gmt":"2026-02-02T11:39:50","slug":"xc4vlx100-10ff1148c","status":"publish","type":"product","link":"https:\/\/www.lxbchip.com\/ru\/products\/xc4vlx100-10ff1148c\/","title":{"rendered":"XC4VLX100-10FF1148C"},"content":{"rendered":"<table id=\"table_1\" class=\"scroll display nowrap data-t data-t wpDataTable wpDataTableID-8 dataTable\" data-described-by=\"table_1_desc\" data-wpdatatable_id=\"8\" aria-describedby=\"table_1_info\">\n<thead>\n<tr>\n<th class=\"wdtheader sort expand column-modelpn sorting\" tabindex=\"0\" colspan=\"1\" rowspan=\"1\" data-class=\"expand\" aria-controls=\"table_1\" aria-label=\" \u041c\u043e\u0434\u0435\u043b\u044c \u043f\/\u043f \u041d\u0435\u043e\u043f\u0440\u0435\u0434\u0435\u043b\u0435\u043d\u043e\">\u041c\u041e\u0414\u0415\u041b\u042c \u041f\/\u041d<\/th>\n<th class=\"wdtheader sort column-series sorting\" tabindex=\"0\" colspan=\"1\" rowspan=\"1\" aria-controls=\"table_1\" aria-label=\" Seriesundefined\">\u0421\u0415\u0420\u0418\u0418<\/th>\n<th class=\"wdtheader sort numdata float column-numberoflabsclbs sorting\" tabindex=\"0\" colspan=\"1\" rowspan=\"1\" aria-controls=\"table_1\" aria-label=\" \u041a\u043e\u043b\u0438\u0447\u0435\u0441\u0442\u0432\u043e \u043b\u0430\u0431\u043e\u0440\u0430\u0442\u043e\u0440\u0438\u0439\/\u041a\u041b\u0411 \u043e\u043f\u0440\u0435\u0434\u0435\u043b\u0435\u043d\u043e\">\u041a\u041e\u041b\u0418\u0427\u0415\u0421\u0422\u0412\u041e \u041b\u0410\u0411\u041e\u0420\u0410\u0422\u041e\u0420\u0418\u0419\/\u041a\u041b\u0411<\/th>\n<th class=\"wdtheader sort numdata float column-speedgrade sorting\" tabindex=\"0\" colspan=\"1\" rowspan=\"1\" aria-controls=\"table_1\" aria-label=\" \u0413\u0440\u0430\u0434\u0443\u0441 \u0441\u043a\u043e\u0440\u043e\u0441\u0442\u0438 \u043e\u043f\u0440\u0435\u0434\u0435\u043b\u0435\u043d\">\u0423\u0420\u041e\u0412\u0415\u041d\u042c \u0421\u041a\u041e\u0420\u041e\u0421\u0422\u0418<\/th>\n<th class=\"wdtheader sort column-numberoflogicelementscells sorting\" tabindex=\"0\" colspan=\"1\" rowspan=\"1\" aria-controls=\"table_1\" aria-label=\" \u041a\u043e\u043b\u0438\u0447\u0435\u0441\u0442\u0432\u043e \u043b\u043e\u0433\u0438\u0447\u0435\u0441\u043a\u0438\u0445 \u044d\u043b\u0435\u043c\u0435\u043d\u0442\u043e\u0432 \/ \u044f\u0447\u0435\u0435\u043a \u043e\u043f\u0440\u0435\u0434\u0435\u043b\u0435\u043d\u043e\">\u041a\u041e\u041b\u0418\u0427\u0415\u0421\u0422\u0412\u041e \u041b\u041e\u0413\u0418\u0427\u0415\u0421\u041a\u0418\u0425 \u042d\u041b\u0415\u041c\u0415\u041d\u0422\u041e\u0412 \/ \u042f\u0427\u0415\u0415\u041a<\/th>\n<th class=\"wdtheader sort column-totalrambits sorting\" tabindex=\"0\" colspan=\"1\" rowspan=\"1\" aria-controls=\"table_1\" aria-label=\" \u041e\u0431\u0449\u0435\u0435 \u043a\u043e\u043b\u0438\u0447\u0435\u0441\u0442\u0432\u043e \u0431\u0438\u0442\u043e\u0432 \u043e\u043f\u0435\u0440\u0430\u0442\u0438\u0432\u043d\u043e\u0439 \u043f\u0430\u043c\u044f\u0442\u0438 \u043e\u043f\u0440\u0435\u0434\u0435\u043b\u044f\u0435\u0442\u0441\u044f\">\u0412\u0421\u0415\u0413\u041e \u0411\u0418\u0422\u041e\u0412 \u041e\u0417\u0423<\/th>\n<th class=\"wdtheader sort numdata integer column-numberofio sorting sorting_asc\" tabindex=\"0\" colspan=\"1\" rowspan=\"1\" aria-controls=\"table_1\" aria-label=\" \u041a\u043e\u043b\u0438\u0447\u0435\u0441\u0442\u0432\u043e \u0432\u0445\u043e\u0434\u043e\u0432\/\u0432\u044b\u0445\u043e\u0434\u043e\u0432 \u043d\u0435 \u043e\u043f\u0440\u0435\u0434\u0435\u043b\u0435\u043d\u043e\" aria-sort=\"ascending\">\u041a\u041e\u041b\u0418\u0427\u0415\u0421\u0422\u0412\u041e \u0412\u0425\u041e\u0414\u041e\u0412\/\u0412\u042b\u0425\u041e\u0414\u041e\u0412<\/th>\n<th class=\"wdtheader sort column-voltagesupply sorting\" tabindex=\"0\" colspan=\"1\" rowspan=\"1\" aria-controls=\"table_1\" aria-label=\" \u041d\u0430\u043f\u0440\u044f\u0436\u0435\u043d\u0438\u0435 - \u043f\u0438\u0442\u0430\u043d\u0438\u0435\u041d\u0435 \u043e\u043f\u0440\u0435\u0434\u0435\u043b\u0435\u043d\u043e\">\u041d\u0410\u041f\u0420\u042f\u0416\u0415\u041d\u0418\u0415 - \u041f\u0418\u0422\u0410\u041d\u0418\u0415<\/th>\n<th class=\"wdtheader sort column-mountingtype sorting\" tabindex=\"0\" colspan=\"1\" rowspan=\"1\" aria-controls=\"table_1\" aria-label=\" \u0422\u0438\u043f \u043a\u0440\u0435\u043f\u043b\u0435\u043d\u0438\u044fundefined\">\u0422\u0418\u041f \u041a\u0420\u0415\u041f\u041b\u0415\u041d\u0418\u042f<\/th>\n<th class=\"wdtheader sort column-operatingtemperature sorting\" tabindex=\"0\" colspan=\"1\" rowspan=\"1\" aria-controls=\"table_1\" aria-label=\" \u0420\u0430\u0431\u043e\u0447\u0430\u044f \u0442\u0435\u043c\u043f\u0435\u0440\u0430\u0442\u0443\u0440\u0430 \u043d\u0435 \u043e\u043f\u0440\u0435\u0434\u0435\u043b\u0435\u043d\u0430\">\u0420\u0410\u0411\u041e\u0427\u0410\u042f \u0422\u0415\u041c\u041f\u0415\u0420\u0410\u0422\u0423\u0420\u0410<\/th>\n<th class=\"wdtheader sort column-packagecase sorting\" tabindex=\"0\" colspan=\"1\" rowspan=\"1\" aria-controls=\"table_1\" aria-label=\" \u0423\u043f\u0430\u043a\u043e\u0432\u043a\u0430 \/ \u041a\u0435\u0439\u0441 \u043e\u043f\u0440\u0435\u0434\u0435\u043b\u0435\u043d\">\u0423\u041f\u0410\u041a\u041e\u0412\u041a\u0410 \/ \u041a\u0415\u0419\u0421<\/th>\n<th class=\"wdtheader sort column-supplierdevicepackage sorting\" tabindex=\"0\" colspan=\"1\" rowspan=\"1\" aria-controls=\"table_1\" aria-label=\" \u041f\u043e\u0441\u0442\u0430\u0432\u0449\u0438\u043a \u041f\u0430\u043a\u0435\u0442 \u0443\u0441\u0442\u0440\u043e\u0439\u0441\u0442\u0432undefined\">\u0423\u041f\u0410\u041a\u041e\u0412\u041a\u0410 \u0423\u0421\u0422\u0420\u041e\u0419\u0421\u0422\u0412\u0410 \u041f\u041e\u0421\u0422\u0410\u0412\u0429\u0418\u041a\u0410<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr class=\"odd\">\n<td class=\"expand column-modelpn\">XC4VLX100-10FF1148C<\/td>\n<td class=\"column-series\">Virtex-4 LX<\/td>\n<td class=\"numdata float column-numberoflabsclbs\">11.520,00<\/td>\n<td class=\"numdata float column-speedgrade\">-10,00<\/td>\n<td class=\"column-numberoflogicelementscells\">99840<\/td>\n<td class=\"column-totalrambits\">4478976<\/td>\n<td class=\"numdata integer column-numberofio sorting_1\">768<\/td>\n<td class=\"column-voltagesupply\">1,14 V ~ 1,26 V<\/td>\n<td class=\"column-mountingtype\">\u041c\u043e\u043d\u0442\u0430\u0436 \u043d\u0430 \u043f\u043e\u0432\u0435\u0440\u0445\u043d\u043e\u0441\u0442\u044c<\/td>\n<td class=\"column-operatingtemperature\">0 \u00b0C ~ +85 \u00b0C (\u043a\u043e\u043c\u043c\u0435\u0440\u0447\u0435\u0441\u043a\u0438\u0439)<\/td>\n<td class=\"column-packagecase\">1148-BBGA (FCBGA)<\/td>\n<td class=\"column-supplierdevicepackage\">1148-FCBGA<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p data-path-to-node=\"3\"><span style=\"color: #000080;\"><b data-path-to-node=\"3\" data-index-in-node=\"0\">XC4VLX100-10FF1148C: High-Density Logic Consolidation for Commercial Computing Platforms<\/b><\/span><\/p>\n<p data-path-to-node=\"4\">\u0421\u0430\u0439\u0442 <b data-path-to-node=\"4\" data-index-in-node=\"4\">XC4VLX100-10FF1148C<\/b> is a high-capacity FPGA within Xilinx\u2019s legendary Virtex\u00ae-4 LX family, specifically engineered for logic-intensive commercial applications. Utilizing the revolutionary <b data-path-to-node=\"4\" data-index-in-node=\"192\">90 \u043d\u043c ASMBL\u2122 (\u0443\u0441\u043e\u0432\u0435\u0440\u0448\u0435\u043d\u0441\u0442\u0432\u043e\u0432\u0430\u043d\u043d\u044b\u0439 \u043a\u0440\u0435\u043c\u043d\u0438\u0435\u0432\u044b\u0439 \u043c\u043e\u0434\u0443\u043b\u044c\u043d\u044b\u0439 \u0431\u043b\u043e\u043a)<\/b> architecture, this device provides a massive <b data-path-to-node=\"4\" data-index-in-node=\"282\">110,592 Logic Cell<\/b> fabric. It is the definitive choice for architects who need to consolidate complex system-level functions\u2014such as multiple soft-core processors, high-bandwidth memory controllers, and extensive custom RTL\u2014into a single, high-reliability silicon footprint.<\/p>\n<p data-path-to-node=\"5\">Operating at a <b data-path-to-node=\"5\" data-index-in-node=\"15\">\u041a\u043e\u043c\u043c\u0435\u0440\u0447\u0435\u0441\u043a\u0438\u0439 \u043a\u043b\u0430\u0441\u0441 (\u043e\u0442 0\u00b0C \u0434\u043e +85\u00b0C)<\/b> temperature range with a <b data-path-to-node=\"5\" data-index-in-node=\"72\">-10 \u043a\u043b\u0430\u0441\u0441 \u0441\u043a\u043e\u0440\u043e\u0441\u0442\u0438<\/b>, it offers a balanced solution for high-end digital signal processing and massive parallel data routing.<\/p>\n<p data-path-to-node=\"6\"><span style=\"color: #000080;\"><b data-path-to-node=\"6\" data-index-in-node=\"0\">Core Engineering Highlights<\/b><\/span><\/p>\n<ul data-path-to-node=\"7\">\n<li>\n<p data-path-to-node=\"7,0,0\"><b data-path-to-node=\"7,0,0\" data-index-in-node=\"0\">Architectural Efficiency:<\/b> The ASMBL architecture allows for a highly uniform distribution of logic, memory, and DSP columns. This reduces routing congestion, a critical advantage when designing high-utilization systems that exceed 80% logic occupancy.<\/p>\n<\/li>\n<li>\n<p data-path-to-node=\"7,1,0\"><b data-path-to-node=\"7,1,0\" data-index-in-node=\"0\">Rich Memory Hierarchy:<\/b> \u0425\u0430\u0440\u0430\u043a\u0442\u0435\u0440\u0438\u0441\u0442\u0438\u043a\u0438 <b data-path-to-node=\"7,1,0\" data-index-in-node=\"32\">4,320 Kb of Block RAM (BRAM)<\/b>. This dual-port memory resources are essential for implementing deep data buffers, localized caching, and high-speed FIFO structures required in streaming video or networking applications.<\/p>\n<\/li>\n<li>\n<p data-path-to-node=\"7,2,0\"><b data-path-to-node=\"7,2,0\" data-index-in-node=\"0\">Massive I\/O Connectivity:<\/b> \u0420\u0430\u0437\u043c\u0435\u0449\u0430\u0435\u0442\u0441\u044f \u0432 <b data-path-to-node=\"7,2,0\" data-index-in-node=\"40\">FF1148 Flip-Chip BGA<\/b> package, the device breaks out <b data-path-to-node=\"7,2,0\" data-index-in-node=\"92\">768 User I\/Os<\/b>. This allows for the simultaneous management of high-width parallel buses, such as dual-bank DDR2 or QDR-II interfaces, without pin-count bottlenecks.<\/p>\n<\/li>\n<li>\n<p data-path-to-node=\"7,3,0\"><b data-path-to-node=\"7,3,0\" data-index-in-node=\"0\">XtremeDSP\u2122 Performance:<\/b> \u0418\u043d\u0442\u0435\u0433\u0440\u0430\u0446\u0438\u044f \u0441 <b data-path-to-node=\"7,3,0\" data-index-in-node=\"40\">96 dedicated DSP48 slices<\/b>. These hard-coded arithmetic blocks handle 18&#215;18 bit multiplications and MAC functions at hardware speeds, freeing up standard logic for control plane tasks.<\/p>\n<\/li>\n<li>\n<p data-path-to-node=\"7,4,0\"><b data-path-to-node=\"7,4,0\" data-index-in-node=\"0\">Precision Clocking (DCM):<\/b> Equipped with advanced <b data-path-to-node=\"7,4,0\" data-index-in-node=\"49\">Digital Clock Managers<\/b> for sub-nanosecond skew control and frequency synthesis, ensuring stable synchronization across complex, multi-clock domain designs.<\/p>\n<\/li>\n<\/ul>\n<hr data-path-to-node=\"8\" \/>\n<p data-path-to-node=\"9\"><span style=\"color: #000080;\"><b data-path-to-node=\"9\" data-index-in-node=\"0\">\u041c\u0430\u0442\u0440\u0438\u0446\u0430 \u0442\u0435\u0445\u043d\u0438\u0447\u0435\u0441\u043a\u0438\u0445 \u0445\u0430\u0440\u0430\u043a\u0442\u0435\u0440\u0438\u0441\u0442\u0438\u043a<\/b><\/span><\/p>\n<table data-path-to-node=\"10\">\n<thead>\n<tr>\n<td><strong>\u0425\u0430\u0440\u0430\u043a\u0442\u0435\u0440\u0438\u0441\u0442\u0438\u043a\u0430<\/strong><\/td>\n<td><strong>\u0422\u0435\u0445\u043d\u0438\u0447\u0435\u0441\u043a\u0438\u0435 \u0445\u0430\u0440\u0430\u043a\u0442\u0435\u0440\u0438\u0441\u0442\u0438\u043a\u0438<\/strong><\/td>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<td><span data-path-to-node=\"10,1,0,0\"><b data-path-to-node=\"10,1,0,0\" data-index-in-node=\"0\">\u041b\u043e\u0433\u0438\u0447\u0435\u0441\u043a\u0438\u0435 \u044f\u0447\u0435\u0439\u043a\u0438<\/b><\/span><\/td>\n<td><span data-path-to-node=\"10,1,1,0\">110,592<\/span><\/td>\n<\/tr>\n<tr>\n<td><span data-path-to-node=\"10,2,0,0\"><b data-path-to-node=\"10,2,0,0\" data-index-in-node=\"0\">CLB Array<\/b><\/span><\/td>\n<td><span data-path-to-node=\"10,2,1,0\">12,480<\/span><\/td>\n<\/tr>\n<tr>\n<td><span data-path-to-node=\"10,3,0,0\"><b data-path-to-node=\"10,3,0,0\" data-index-in-node=\"0\">\u0412\u0441\u0435\u0433\u043e \u0431\u043b\u043e\u043a\u043e\u0432 \u043e\u043f\u0435\u0440\u0430\u0442\u0438\u0432\u043d\u043e\u0439 \u043f\u0430\u043c\u044f\u0442\u0438<\/b><\/span><\/td>\n<td><span data-path-to-node=\"10,3,1,0\">4 320 \u041a\u0431<\/span><\/td>\n<\/tr>\n<tr>\n<td><span data-path-to-node=\"10,4,0,0\"><b data-path-to-node=\"10,4,0,0\" data-index-in-node=\"0\">\u041b\u043e\u043c\u0442\u0438\u043a\u0438 DSP48<\/b><\/span><\/td>\n<td><span data-path-to-node=\"10,4,1,0\">96<\/span><\/td>\n<\/tr>\n<tr>\n<td><span data-path-to-node=\"10,5,0,0\"><b data-path-to-node=\"10,5,0,0\" data-index-in-node=\"0\">\u041f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u0435\u043b\u044c\u0441\u043a\u0438\u0435 \u0432\u0445\u043e\u0434\u044b\/\u0432\u044b\u0445\u043e\u0434\u044b<\/b><\/span><\/td>\n<td><span data-path-to-node=\"10,5,1,0\">768<\/span><\/td>\n<\/tr>\n<tr>\n<td><span data-path-to-node=\"10,6,0,0\"><b data-path-to-node=\"10,6,0,0\" data-index-in-node=\"0\">\u0421\u0442\u0435\u043f\u0435\u043d\u044c \u0441\u043a\u043e\u0440\u043e\u0441\u0442\u0438<\/b><\/span><\/td>\n<td><span data-path-to-node=\"10,6,1,0\">-10 (\u0441\u0442\u0430\u043d\u0434\u0430\u0440\u0442\u043d\u043e\u0435 \u0438\u0441\u043f\u043e\u043b\u043d\u0435\u043d\u0438\u0435)<\/span><\/td>\n<\/tr>\n<tr>\n<td><span data-path-to-node=\"10,7,0,0\"><b data-path-to-node=\"10,7,0,0\" data-index-in-node=\"0\">\u0422\u0435\u043c\u043f\u0435\u0440\u0430\u0442\u0443\u0440\u043d\u044b\u0439 \u043a\u043b\u0430\u0441\u0441<\/b><\/span><\/td>\n<td><span data-path-to-node=\"10,7,1,0\">\u041a\u043e\u043c\u043c\u0435\u0440\u0447\u0435\u0441\u043a\u0438\u0439 (\u043e\u0442 0\u00b0C \u0434\u043e +85\u00b0C)<\/span><\/td>\n<\/tr>\n<tr>\n<td><span data-path-to-node=\"10,8,0,0\"><b data-path-to-node=\"10,8,0,0\" data-index-in-node=\"0\">\u041f\u0430\u043a\u0435\u0442<\/b><\/span><\/td>\n<td><span data-path-to-node=\"10,8,1,0\">FF1148 (Flip-Chip BGA)<\/span><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<hr data-path-to-node=\"11\" \/>\n<p data-path-to-node=\"12\"><span style=\"color: #000080;\"><b data-path-to-node=\"12\" data-index-in-node=\"0\">Hardware Architect\u2019s Perspective: Why Specify the LX100-10C?<\/b><\/span><\/p>\n<p data-path-to-node=\"13\"><b data-path-to-node=\"13\" data-index-in-node=\"0\">1. Predictable Timing Closure<\/b><\/p>\n<p data-path-to-node=\"13\">One of the primary reasons engineers stay with the Virtex-4 LX100 is its predictable routing fabric. Unlike newer, more congested architectures, the LX100 provides consistent timing models that allow for faster design iterations and &#8220;right-the-first-time&#8221; silicon behavior.<\/p>\n<p data-path-to-node=\"14\"><b data-path-to-node=\"14\" data-index-in-node=\"0\">2. Superior Signal Integrity<\/b><\/p>\n<p data-path-to-node=\"14\">\u0421\u0430\u0439\u0442 <b data-path-to-node=\"14\" data-index-in-node=\"33\">FF1148 Flip-Chip package<\/b> is specifically designed to minimize parasitic inductance. With a dense distribution of VCC and GND pins, it suppresses <b data-path-to-node=\"14\" data-index-in-node=\"178\">Simultaneous Switching Noise (SSN)<\/b>, ensuring clean signal eyes for high-speed differential pairs (LVDS\/HSTL).<\/p>\n<p data-path-to-node=\"15\"><b data-path-to-node=\"15\" data-index-in-node=\"0\">3. Maturity and Stability<\/b><\/p>\n<p data-path-to-node=\"15\">For commercial products with long lifecycles\u2014such as medical imaging backplanes or high-end broadcasting gear\u2014the LX100-10C offers a proven track record of field reliability and a well-documented toolchain, reducing the risk of unexpected architectural bugs.<\/p>\n<hr data-path-to-node=\"16\" \/>\n<p data-path-to-node=\"17\"><span style=\"color: #000080;\"><b data-path-to-node=\"17\" data-index-in-node=\"0\">Ideal Use Cases<\/b><\/span><\/p>\n<ul data-path-to-node=\"18\">\n<li>\n<p data-path-to-node=\"18,0,0\"><b data-path-to-node=\"18,0,0\" data-index-in-node=\"0\">Broadcasting:<\/b> Real-time format conversion and professional-grade video switching.<\/p>\n<\/li>\n<li>\n<p data-path-to-node=\"18,1,0\"><b data-path-to-node=\"18,1,0\" data-index-in-node=\"0\">\u041c\u0435\u0434\u0438\u0446\u0438\u043d\u0441\u043a\u0438\u0435 \u0441\u0438\u0441\u0442\u0435\u043c\u044b:<\/b> Advanced MRI data acquisition and real-time image reconstruction.<\/p>\n<\/li>\n<li>\n<p data-path-to-node=\"18,2,0\"><b data-path-to-node=\"18,2,0\" data-index-in-node=\"0\">Test &amp; Measurement:<\/b> Logic analyzer front-ends and high-speed pattern generation.<\/p>\n<\/li>\n<li>\n<p data-path-to-node=\"18,3,0\"><b data-path-to-node=\"18,3,0\" data-index-in-node=\"0\">\u041a\u043e\u043c\u043c\u0443\u043d\u0438\u043a\u0430\u0446\u0438\u0438:<\/b> High-speed protocol conversion and localized switching fabrics.<\/p>\n<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"<p><strong>\u041f\u0440\u043e\u0438\u0437\u0432\u043e\u0434\u0438\u0442\u0435\u043b\u044c:<\/strong> Xilinx<br \/>\n<strong>\u041b\u043e\u0433\u0438\u0447\u0435\u0441\u043a\u0438\u0435 \u044f\u0447\u0435\u0439\u043a\u0438:<\/strong> 110,592<br \/>\n<strong>\u041b\u043e\u0433\u0438\u0447\u0435\u0441\u043a\u0438\u0435 \u0441\u0440\u0435\u0437\u044b:<\/strong> 49,152 (approx)<br \/>\n<strong>\u0412\u0441\u0442\u0440\u043e\u0435\u043d\u043d\u0430\u044f \u043e\u043f\u0435\u0440\u0430\u0442\u0438\u0432\u043d\u0430\u044f \u043f\u0430\u043c\u044f\u0442\u044c (eRAM):<\/strong> 4,320 Kb (240 \u00d7 18Kb Block RAM)<br \/>\n<strong>\u0423\u043f\u0430\u043a\u043e\u0432\u043a\u0430:<\/strong> FF1148 (Fine-Pitch BGA)<br \/>\n<strong>\u0420\u0430\u0431\u043e\u0447\u0430\u044f \u0442\u0435\u043c\u043f\u0435\u0440\u0430\u0442\u0443\u0440\u0430:<\/strong> \u041a\u043e\u043c\u043c\u0435\u0440\u0447\u0435\u0441\u043a\u0438\u0439 (\u043e\u0442 0\u00b0C \u0434\u043e +85\u00b0C)<\/p>","protected":false},"featured_media":6090,"template":"","meta":{"_acf_changed":false},"product_brand":[],"product_cat":[21],"product_tag":[],"class_list":["post-6662","product","type-product","status-publish","has-post-thumbnail","product_cat-xilinx","first","instock","shipping-taxable","product-type-simple"],"acf":[],"aioseo_notices":[],"_links":{"self":[{"href":"https:\/\/www.lxbchip.com\/ru\/wp-json\/wp\/v2\/product\/6662","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.lxbchip.com\/ru\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/www.lxbchip.com\/ru\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/www.lxbchip.com\/ru\/wp-json\/wp\/v2\/media\/6090"}],"wp:attachment":[{"href":"https:\/\/www.lxbchip.com\/ru\/wp-json\/wp\/v2\/media?parent=6662"}],"wp:term":[{"taxonomy":"product_brand","embeddable":true,"href":"https:\/\/www.lxbchip.com\/ru\/wp-json\/wp\/v2\/product_brand?post=6662"},{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/www.lxbchip.com\/ru\/wp-json\/wp\/v2\/product_cat?post=6662"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/www.lxbchip.com\/ru\/wp-json\/wp\/v2\/product_tag?post=6662"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}