{"id":11482,"date":"2026-03-05T12:16:42","date_gmt":"2026-03-05T04:16:42","guid":{"rendered":"https:\/\/www.lxbchip.com\/?post_type=product&p=11482"},"modified":"2026-06-09T02:06:48","modified_gmt":"2026-06-08T18:06:48","slug":"stm32f407zet6","status":"publish","type":"product","link":"https:\/\/www.lxbchip.com\/ar\/products\/stm32f407zet6\/","title":{"rendered":"STM32F407ZET6"},"content":{"rendered":"
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The STM32F405xx and STM32F407xx family is based on the high-performance Arm\u00ae<\/sup>\u00a0\u0643\u0648\u0631\u062a\u064a\u0643\u0633\u00ae<\/sup>-M4 32-bit RISC core operating at a frequency of up to 168 MHz. The Cortex\u00ae<\/sup>-M4 core features a floating-point unit (FPU) single precision which supports all Arm single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security.<\/p>\n

The STM32F405xx and STM32F407xx family incorporates high-speed embedded memories (flash memory up to 1 Mbyte, up to 192 Kbytes of SRAM), up to 4 Kbytes of backup SRAM, and an extensive range of enhanced I\/Os and peripherals connected to two APB buses, three AHB buses and a 32-bit multi-AHB bus matrix.<\/p>\n

All devices offer three 12-bit ADCs, two DACs, a low-power RTC, 12 general-purpose 16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers. a true random number generator (RNG). They also feature standard and advanced communication interfaces.<\/p>\n<\/div>\n<\/div>\n<\/div>\n

\u0627\u0644\u0645\u064a\u0632\u0627\u062a \u0627\u0644\u0631\u0626\u064a\u0633\u064a\u0629<\/a><\/div>\n
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\u0627\u0644\u0645\u064a\u0632\u0627\u062a \u0627\u0644\u0631\u0626\u064a\u0633\u064a\u0629<\/caption>\n
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  • Includes ST state-of-the-art patented technology<\/li>\n
  • \u0627\u0644\u0646\u0648\u0627\u0629: Arm\u00ae<\/sup>\u00a0\u0643\u0648\u0631\u0643\u0633 32 \u0628\u062a\u00ae<\/sup>-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator) allowing 0-wait state execution from flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS\/1.25 DMIPS\/MHz (Dhrystone 2.1), and DSP instructions<\/li>\n
  • \u0630\u0643\u0631\u064a\u0627\u062a\n
      \n
    • Up to 1 Mbyte of flash memory<\/li>\n
    • Up to 192+4 Kbytes of SRAM including 64-Kbyte of CCM (core coupled memory) data RAM<\/li>\n
    • 512 bytes of OTP memory<\/li>\n
    • Flexible static memory controller supporting CompactFlash\u2122, SRAM, PSRAM, NOR and NAND memories<\/li>\n<\/ul>\n<\/li>\n
    • \u0648\u0627\u062c\u0647\u0629 \u0645\u062a\u0648\u0627\u0632\u064a\u0629 \u0644\u0634\u0627\u0634\u0629 LCD\u060c \u0623\u0648\u0636\u0627\u0639 8080\/6800<\/li>\n
    • Clock, reset, and supply management\n
        \n
      • 1.8 V to 3.6 V application supply and I\/Os<\/li>\n
      • POR \u0648 PDR \u0648 PVD \u0648 BOR<\/li>\n
      • 4-to-26 MHz crystal oscillator<\/li>\n
      • \u0645\u0630\u0628\u0630\u0628 \u062f\u0627\u062e\u0644\u064a \u0628\u062a\u0631\u062f\u062f 16 \u0645\u064a\u062c\u0627\u0647\u0631\u062a\u0632 \u062a\u0645 \u0636\u0628\u0637\u0647 \u0641\u064a \u0627\u0644\u0645\u0635\u0646\u0639 (\u0628\u062f\u0642\u0629 1%)<\/li>\n
      • \u0645\u0630\u0628\u0630\u0628 \u0628\u062a\u0631\u062f\u062f 32 \u0643\u064a\u0644\u0648\u0647\u0631\u062a\u0632 \u0644\u0633\u0627\u0639\u0629 \u0627\u0644\u0648\u0642\u062a \u0627\u0644\u062d\u0642\u064a\u0642\u064a (RTC) \u0645\u0632\u0648\u062f \u0628\u062e\u0627\u0635\u064a\u0629 \u0627\u0644\u0645\u0639\u0627\u064a\u0631\u0629<\/li>\n
      • \u0648\u062d\u062f\u0629 \u062a\u062d\u0643\u0645 \u062f\u0627\u062e\u0644\u064a\u0629 \u0628\u062a\u0631\u062f\u062f 32 \u0643\u064a\u0644\u0648\u0647\u0631\u062a\u0632 \u0645\u0632\u0648\u062f\u0629 \u0628\u062e\u0627\u0635\u064a\u0629 \u0627\u0644\u0645\u0639\u0627\u064a\u0631\u0629<\/li>\n<\/ul>\n<\/li>\n
      • Low-power operation\n
          \n
        • Sleep, Stop, and Standby modes<\/li>\n
        • VBAT<\/sub>\u00a0supply for RTC, 20\u00d732-bit backup registers + optional 4 KB backup SRAM<\/li>\n<\/ul>\n<\/li>\n
        • 3\u00d712-bit, 2.4 MSPS A\/D converters: up to 24 channels and 7.2 MSPS in triple interleaved mode<\/li>\n
        • 2\u00d712-bit D\/A converters<\/li>\n
        • DMA \u0644\u0644\u0623\u063a\u0631\u0627\u0636 \u0627\u0644\u0639\u0627\u0645\u0629: \u0648\u062d\u062f\u0629 \u062a\u062d\u0643\u0645 DMA \u0630\u0627\u062a 16 \u0645\u0633\u0627\u0631\u064b\u0627 \u0645\u0632\u0648\u062f\u0629 \u0628\u0630\u0627\u0643\u0631\u0627\u062a FIFO \u0648\u062f\u0639\u0645 \u0627\u0644\u0625\u0631\u0633\u0627\u0644 \u0627\u0644\u0645\u062a\u062a\u0627\u0628\u0639<\/li>\n
        • Up to 17 timers: up to twelve 16-bit and two 32-bit timers up to 168 MHz, each with up to 4 IC\/OC\/PWM or pulse counter and quadrature (incremental) encoder input<\/li>\n
        • \u0648\u0636\u0639 \u0627\u0644\u062a\u0635\u062d\u064a\u062d\n
            \n
          • Serial wire debug (SWD) & JTAG interfaces<\/li>\n
          • Cortex-M4 Embedded Trace Macrocell\u2122<\/li>\n<\/ul>\n<\/li>\n
          • Up to 140 I\/O ports with interrupt capability\n
              \n
            • Up to 136 fast I\/Os up to 84 MHz<\/li>\n
            • Up to 138 5 V-tolerant I\/Os<\/li>\n<\/ul>\n<\/li>\n
            • Up to 15 communication interfaces\n
                \n
              • Up to 3 \u00d7 I2<\/sup>\u0648\u0627\u062c\u0647\u0627\u062a C (SMBus\/PMBus)<\/li>\n
              • Up to 4 USARTs\/2 UARTs (10.5 Mbit\/s, ISO 7816 interface, LIN, IrDA, modem control)<\/li>\n
              • Up to 3 SPIs (42 Mbits\/s), 2 with muxed full-duplex I2<\/sup>S to achieve audio class accuracy via internal audio PLL or external clock<\/li>\n
              • 2 \u00d7 CAN interfaces (2.0B Active)<\/li>\n
              • \u0648\u0627\u062c\u0647\u0629 SDIO<\/li>\n<\/ul>\n<\/li>\n
              • \u0625\u0645\u0643\u0627\u0646\u064a\u0627\u062a \u0627\u062a\u0635\u0627\u0644 \u0645\u062a\u0637\u0648\u0631\u0629\n
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                • \u0648\u062d\u062f\u0629 \u062a\u062d\u0643\u0645 USB 2.0 \u0639\u0627\u0644\u064a\u0629 \u0627\u0644\u0633\u0631\u0639\u0629 \u0644\u0644\u0623\u062c\u0647\u0632\u0629\/\u0627\u0644\u0645\u0636\u064a\u0641\/OTG \u0645\u0632\u0648\u062f\u0629 \u0628\u0648\u062d\u062f\u0629 PHY \u0645\u062f\u0645\u062c\u0629 \u0641\u064a \u0627\u0644\u0631\u0642\u0627\u0642\u0629<\/li>\n
                • \u0648\u062d\u062f\u0629 \u062a\u062d\u0643\u0645 USB 2.0 \u0639\u0627\u0644\u064a\u0629 \u0627\u0644\u0633\u0631\u0639\u0629\/\u0643\u0627\u0645\u0644\u0629 \u0627\u0644\u0633\u0631\u0639\u0629 \u0644\u0644\u0623\u062c\u0647\u0632\u0629\/\u0627\u0644\u0645\u0636\u064a\u0641\/OTG \u0645\u0632\u0648\u062f\u0629 \u0628\u0648\u062d\u062f\u0629 DMA \u0645\u062e\u0635\u0635\u0629\u060c \u0648\u0648\u062d\u062f\u0629 PHY \u0643\u0627\u0645\u0644\u0629 \u0627\u0644\u0633\u0631\u0639\u0629 \u0645\u062f\u0645\u062c\u0629 \u0641\u064a \u0627\u0644\u0631\u0642\u0627\u0642\u0629\u060c \u0648\u0648\u062d\u062f\u0629 ULPI<\/li>\n
                • 10\/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII\/RMII<\/li>\n<\/ul>\n<\/li>\n
                • \u0648\u0627\u062c\u0647\u0629 \u0643\u0627\u0645\u064a\u0631\u0627 \u0645\u062a\u0648\u0627\u0632\u064a\u0629 \u0645\u0646 8 \u0625\u0644\u0649 14 \u0628\u062a \u0628\u0633\u0631\u0639\u0629 \u062a\u0635\u0644 \u0625\u0644\u0649 54 \u0645\u064a\u063a\u0627\u0628\u0627\u064a\u062a \u0641\u064a \u0627\u0644\u062b\u0627\u0646\u064a\u0629<\/li>\n
                • True random number generator<\/li>\n
                • \u0648\u062d\u062f\u0629 \u062d\u0633\u0627\u0628 CRC<\/li>\n
                • \u0645\u0639\u0631\u0641 \u0641\u0631\u064a\u062f \u0645\u0646 96 \u0628\u062a<\/li>\n
                • RTC: \u062f\u0642\u0629 \u0623\u0642\u0644 \u0645\u0646 \u062b\u0627\u0646\u064a\u0629\u060c \u062a\u0642\u0648\u064a\u0645 \u0645\u062f\u0645\u062c \u0641\u064a \u0627\u0644\u062c\u0647\u0627\u0632<\/li>\n
                • All packages are ECOPACK2 compliant<\/li>\n<\/ul>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/div>\n<\/div>","protected":false},"excerpt":{"rendered":"

                  The STM32F405xx and STM32F407xx family is based on the high-performance Arm\u00ae\u00a0Cortex\u00ae-M4 32-bit RISC core operating at a frequency of up<\/p>","protected":false},"featured_media":12617,"template":"","meta":{"_acf_changed":false},"product_brand":[],"product_cat":[118],"product_tag":[],"class_list":["post-11482","product","type-product","status-publish","has-post-thumbnail","product_cat-st","first","instock","shipping-taxable","product-type-simple"],"acf":[],"aioseo_notices":[],"_links":{"self":[{"href":"https:\/\/www.lxbchip.com\/ar\/wp-json\/wp\/v2\/product\/11482","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.lxbchip.com\/ar\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/www.lxbchip.com\/ar\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/www.lxbchip.com\/ar\/wp-json\/wp\/v2\/media\/12617"}],"wp:attachment":[{"href":"https:\/\/www.lxbchip.com\/ar\/wp-json\/wp\/v2\/media?parent=11482"}],"wp:term":[{"taxonomy":"product_brand","embeddable":true,"href":"https:\/\/www.lxbchip.com\/ar\/wp-json\/wp\/v2\/product_brand?post=11482"},{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/www.lxbchip.com\/ar\/wp-json\/wp\/v2\/product_cat?post=11482"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/www.lxbchip.com\/ar\/wp-json\/wp\/v2\/product_tag?post=11482"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}